Bus Master Mode of PCI-Bus. Part IV

Use the parameter “Master Prefetch and Posting” (value Enabled) to speed up the process of sending the data. This parameter allows simultaneously using the prefetch mode and a buffer of posted record for any master-device.

Use the parameter “CPU Mstr Post-WR Burst Mode” to turn on the high-speed packet mode of transmission information from a buffer of posted record. This value may have two values: Enabled and Disabled. If packing for information transmission is allowed, the same address is given to each data block that increases the system productivity.

Another opportunity to reduce the time spent by master-devices for operation with PCI-bus is reducing delays of waiting responses from a device and the time during which a processor controls this bus. In the first case the parameter “CPU Mstr DEVSEL# Time-out” is used. It may have the following values that determine the delay as a number of cycles of PCI-bus: 3 PCUCLK, 4 PCICLK, 5 PCICLK and 6 PCICLK. But decreased value of this parameter may lead to failures in system operation. Use the parameter “Master Retry Timer” to set the time during which the processor may dominate in the bus operation. This parameter may have the values stated in the cycles of PCI-bus: 10 PCICLK, 18 PCICLK, 34 PCICLK and 66 PCICLK.