ISA Bus. Part II

An access to ISA-bus is carried out in the following way: if there is a master-device, it is the dominant one while the rest devices wait for the bus release and then all received requests are allocated by using the bus controller. Use the parameter “Slave Wait States” (ISA Wait States) to indicate a delay while waiting an access to a bus. This parameter may have values “4WS” (4ISACLKs) and “5WS” (5ISACLKs) that indicate four or five waiting states in the bus frequencies accordingly.

By default the frequency of ISA-bus is equal to 8,33 MHz. But this value can be changed using the parameter “ISA Bus Clock” (ISA Clock, ISA Bus Clock Frequency, ISA Clock Divisor, AT Bus Clock Selection, AT Bus Clock Source). The frequency of this bus is set via the southern bridge of a chipset and depends on the frequency of PCI-bus which, in turn, depends on the frequency of FSB-bus (processor-chipset). So, this parameter has got the values that are multiple of the frequency of PCI-bus, for example PCICLK/4 or PCICLK/3.